A phase-locked loop is an electronic circuit that controls an oscillator in order to lock the phase of an output signal to the phase of a reference signal. Generally, a phase-locked loop (PLL) feedback system includes a voltage-controlled oscillator and a phase comparator. The oscillator frequency (or phase) accurately tracks the frequency of an input signal, or an integer multiple of the frequency of the input signal.
A phase-locked loop circuit can be used to generate a stable high frequency output signal from a fixed low-frequency signal. The phase-locked loop circuit generates an output signal that is a multiple of the input signal by using a frequency divider in the feedback stage of the loop. The frequency divider divides the output signal from the oscillator before feeding the signal to the phase comparator. When the circuit is in a “locked” state, the output signal has a frequency that is an integer multiple of the frequency of the input signal. After the frequency divider demultiplies the output signal, the feedback signal fed to the phase comparator has the same frequency as the input signal and the error from the phase comparator is zero. In this manner, the output signal from the phase-locked loop circuit has a frequency that is an integer multiple of the frequency of the input signal.
A problem with conventional phase-locked loop circuits is that the conventional phase-locked loop circuits cannot predict the phase of an output signal without an extended observation. Even though the output frequency of a locked signal is stable relative to the input frequency, the phase of the output signal may be skewed relative to the input signal. A phase-locked loop produces an edge in an output signal when an input signal produces an edge, but the circuit is unpredictable as to whether the corresponding output edge is rising or falling. Observation of the PLL output signal enables other circuitry in a system implementing the PLL to know which phase the PLL-clocked circuit is in, but an actual estimate cannot be made without observation. The unpredictable timing of a phase-locked loop circuit causes difficulty in creating test vectors for automated production testing of an integrated circuit that uses PLL for clocking.